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Memristor-based hardware accelerators for artificial intelligence

Nature Reviews Electrical Engineering (2024)Cite this article

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Abstract

Satisfying the rapid evolution of artificial intelligence (AI) algorithms requires exponential growth in computing resources, which, in turn, presents huge challenges for deploying AI models on hardware. Memristor-based hardware accelerators provide a promising solution to the energy efficiency and latency issues in large AI model deployments. The non-volatility of memristive devices facilitates in-memory computing, in which computing occurs within memory cells where data are stored. This approach eliminates the constant data shuttling between the processing and memory units found in the von Neumann architecture, resulting in substantial time and energy savings. The recent surge of research and development in this field indicates a pivotal transition of memristor technology from proof-of-concept demonstrations to commercial products that accelerate AI models across various applications. In this Review, we survey the latest progress in memristive crossbar arrays, peripheral circuits, architectures, hardware–software co-designs and system implementations for memristor-based hardware accelerators. We discuss how these research efforts bridge the gap between memristive devices and energy-efficient accelerators for AI. Finally, we summarize the key remaining issues and propose potential pathways to future hardware accelerators with low latency and high energy efficiency, emphasizing the technology scale-up and commercialization for large-scale AI applications.

Key points

  • Analogue in-memory computing based on memristive devices provides energy-efficient and low-latency hardware solutions for the rapid development of ubiquitous artificial intelligence (AI) applications.

  • Memristive crossbar arrays, evolving from 2D to 3D structure, enable parallel vector–matrix multiplications, the most computing-intensive operations in artificial neural network models, serving as fundamental building blocks of hardware accelerators for AI.

  • Complementary metal-oxide-semiconductor (CMOS)-based peripherals for analogue–digital conversions and programming of memristive crossbar arrays have been designed to strike a balance between bit precisions of inputs, weights and outputs, computing latency, area efficiency and energy efficiency of integrated memristor-based accelerators.

  • The evolution of memristor-based hardware accelerators is showcased from proof-of-concept demonstrations in single memristive crossbar arrays with discrete components to industry-level AI model implementations on multicore chips with integrated peripherals, because of increased on-chip computing resources and advancing CMOS peripheral designs.

  • The hardware–software co-design, involving device modelling, hardware-aware training, circuit and system simulation and multicore architecture demonstration, has been explored aimed at enhancing the performance of memristor-based hardware accelerators but is still in its early phase.

  • A hardware–software co-design and co-optimization ecosystem, including memristive device engineering, CMOS circuit design, system architecture development, learning algorithm optimization, and so on, is a pressing need to push memristive technology from research demonstrations to market products.

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Fig. 1: Analogue in-memory computing based on memristive devices for artificial intelligence acceleration.
Fig. 2: The designs of memristive cells and crossbar arrays for analogue matrix operations.
Fig. 3: Different in-memory computing schemes and hardware architectures.
Fig. 4: The computing performance and hardware resource breakdown of published memristive macros and integrated chips.
Fig. 5: Hardware–software co-design and co-optimization diagram for memristor-based hardware accelerator.

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Acknowledgements

The authors acknowledge the partial support by the Army Research Office (grant no. W911NF-23-2-0014), the Office of Naval Research (grant no. N00014-23-1-2021), the National Science Foundation (contract no. 2023752) and the Air Force Office of Scientific Research (contract no. FA9550-19-1-0213).

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA

    Yi Huang & Qiangfei Xia

  2. IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA

    Takashi Ando

  3. IBM Research Europe, Rüschlikon, Switzerland

    Abu Sebastian

  4. National Tsing Hua University, Hsinchu, Taiwan, Republic of China

    Meng-Fan Chang

  5. Ming Hsieh Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA

    J. Joshua Yang

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  1. Yi Huang
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Contributions

Y.H. and Q.X. researched data for the article. All authors contributed substantially to discussion of the content. Y.H. and Q.X. wrote the article. All authors edited the manuscript before submission.

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Correspondence to Qiangfei Xia.

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Q.X. and J.J.Y. are co-founders and paid consultants of TetraMem.

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Huang, Y., Ando, T., Sebastian, A. et al. Memristor-based hardware accelerators for artificial intelligence. Nat Rev Electr Eng (2024). https://doi.org/10.1038/s44287-024-00037-6

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